1 HIP1020 single, double or triple-output hot plug controller the HIP1020 applies a linear voltage ramp to the gates of any combination of 3.3v, 5v, and 12v mosfets. the internal charge pump doubles a 12v bias or triples a 5v bias to deliver the high-side drive capability required when using more cost-effective n-channel mosfets. the 5v/ms ramp rate is controlled internally and is the proper value to turn on most devices within the device-bay-speci?d di/dt limit. if a slower rate is required, the internally-determined ramp rate can be over ridden using an optional external capacitor. when vcc = 12v, the charge pump ramps the voltage on hgate from zero to 22v in about 4ms. this allows either a standard or a logic-level mosfet to become fully enhanced when used as a high-side switch for 12v power control. the voltage on lgate ramps from zero to 16v allowing the simultaneous control of 3.3v and/or 5v mosfets. when vcc = 5v, the charge pump enters voltage-tripler mode. the voltage on hgate ramps from zero to 12.5v in about 3ms while lgate ramps to 12.0v. this mode is ideal for control of high-side mosfet switches used in 3.3v and 5v power switching when 12v bias is not available. features rise time controlled to device-bay speci?ations no additional components required internal charge pump drives n-channel mosfets drives any combination of one, two or three outputs internally-controlled turn-on ramp - optional capacitor selects slower rates prevents false turn on during hot insertion operates using 12v or 5v bias improves device bay peripheral size cost and complexity - minimal component count - tiny 5-pin sot23 package controls standard and logic-level mosfets compatible with ttl and 3.3v logic devices shutdown current . . . . . . . . . . . . . . . . . . . . . . . . . . < 1 a operating current. . . . . . . . . . . . . . . . . . . . . . . . . . < 3ma applications device bay peripherals hot plug control power distribution control pinout HIP1020 (sot23) top view ordering information part number temp. range ( o c) package pkg. no. HIP1020ck-t 0 to 70 5 ld sot23 tape and reel p5.064 4 5 3 2 1 vcc gnd lgate en hgate typical applications figure 1a. device-bay hot plug controller with vcc = 12v figure 1b. device-bay hot plug controller with vcc = 5v 1 2 34 5 c1 charge pump HIP1020 enable optional v 12,out v 5,out v 33,out v 33 v 5 v 12 1 2 34 5 c1 charge pump HIP1020 enable optional v 5,out v 33,out v 33 v 5 data sheet august 1999 file number 4601.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | copyright intersil corporation 1999 the 68hc05 microcontroller is manufactured under license from motorola, inc.
2 pin descriptions pin symbol function description 1 vcc bias supply connect this pin to either a 12v or a 5v source. the HIP1020 detects the bias-voltage level at pin 1 and decides whether to operate as a voltage-doubler or a voltage-tripler. consequently, it is not recommended to operate with bias voltages between 5v ( 10%) and 12v ( 10%). in the absence of an enable signal at pin 5, the current into pin 1 is less than 1 a. it is necessary for voltage to be present at pin 1 prior to applying an enable signal at pin 5. 2 gnd ground connect to the negative rail of the supply that is connected to pin 1. 3 lgate gate driver for the 5v and/or 3.3v mosfet(s) when vcc = 12v, connect this pin to the gate(s) of the 5v and/or 3.3v mosfets. when vcc = 5v, connect this pin to the gate of a 3.3v mosfet. upon a rising edge on en (pin 5), the voltage on this pin will ramp linearly to ~16v when vcc = 12v and ~12v when vcc = 5v. an internal dv/dt activated clamp shunts coupled noise to ground preventing unintended turn on at either output. the internal dv/dt-activated clamp also protects pin 5. 4 hgate 12v or 5v mosfet gate driver when vcc = 12v, connect this pin to the gate of the 12v mosfet. when vcc = 5v, connect this pin to the gate of the 5v mosfet. upon a rising edge on en (pin 5), the voltage on this pin will ramp linearly to ~22v when vcc = 12v and ~13v when vcc = 5v. 5 en enable connect a ttl or 3.3v logic signal to this pin to control the outputs at pins 3 and 4. a rising edge on pin 5 initiates the linear voltage ramps at pins 3 and 4. be sure that the device driving en does not enter a high-impedance state when enabling is not desired and that it? maximum rise time does not exceed 100 s. HIP1020
3 absolute maximum ratings thermal information supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5v hgate current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma lgate current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma en voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0v operating conditions supply voltage, vcc . . . . . . . . . . . . . . . . . . .5v 10% or 12v 10% temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, note 1) ja ( o c/w) sot23/5l package . . . . . . . . . . . . . . . . . . . . . . . . . 240 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?ations parameter symbol test conditions min typ max units vcc supply current operating supply i cc,12 v en = 5v,v cc = 12v - 1.6 2.3 ma operating supply i cc,5 v en = 5v, v cc = 5v - 0.77 1.1 ma shutdown supply i shdn v en = 0v - - 1 a gate control outputs hgate dv/dt (no external capacitor) dv/dt v cc = 12v 2.5 5 8.5 v / ms v cc = 5v 2.4 5 7.2 v / ms lgate dv/dt (no external capacitor) dv/dt v cc = 12v 2.5 5 8.5 v / ms v cc = 5v 2.6 5 7.4 v / ms hgate pull-up current i hgate v cc = 12v, v hgate = 19v 7.6 13.4 18.5 a v cc = 5v, v hgate = 9.5v 7.6 12.3 18.5 a hgate output voltage v hgate v cc = 12v 20.7 21.8 22.8 v v cc = 5v 11.6 12.5 13.4 v lgate output voltage v lgate v cc = 12v 15.2 16.3 18.3 v v cc = 5v 10.6 11.7 12.9 v enable input threshold voltage v en v cc = 12v 1 - 2.4 v enable current i en v en = 5v - - 1 a HIP1020
4 application information the HIP1020 was designed speci?ally to address the requirements of device bay peripherals. the small package, low cost and integrated features make it the ideal component for high-side power control of all three device-bay rail voltages without using any additional components except for the switching mosfets themselves. the integrated charge pump supplies suf?ient voltage to fully enhance the lower- cost n-channel power mosfets, and the internally- controlled turn-on ramp provides soft switching for all types of loads. although the HIP1020 was developed with device bay in mind, it has the versatility to perform in any situation where low-cost load switching is required. mosfet selection for device bay peripherals when selecting power mosfets for device bay (or any similar application), two major concerns are the voltage drop across the mosfet and the thermal requirements imposed by the particular application. voltage drop across the mosfet is controlled by its on-state resistance, r ds(on) , and the peak current through the device, while the thermal requirements are determined by several factors including ambient temperature, amount of air ?w if any, area of the copper mounting pad, the thermal characteristics of the mosfet and its package, and the average current through the mosfet. typical performance curves figure 2. hgate (pin 4) turning on with vcc = 12v figure 3. lgate (pin 3) turning on with vcc = 12v figure 4. hgate (pin 4) turning on with vcc = 5v figure 5. lgate (pin 3)turning on with vcc = 5v notes: device is enabled at 10 milliseconds. 2. pins 3 and 4 are unconnected. 3. pins 3 and 4 are connected to the gates of ?ypical?high-performance n-channel mosfets. 0 -5 5 10 15 20 25 0 10 304050 20 milliseconds volts 22nf note 3 note 2 c1 = 22nf c1 = 10nf 0 -5 5 10 15 20 25 010 304050 20 milliseconds volts note 3 note 2 c1 = 22nf c1 = 10nf -5 0 5 10 15 0 10 304050 20 milliseconds volts note 3 note 2 c1 = 22nf c1 = 10nf 0 1020304050 -5 0 5 10 15 milliseconds volts note 3 note 2 c1 = 22nf c1 = 10nf HIP1020
5 the mosfets in table 1 were selected based on the assumption that at most 2% the of the 5v or 3.3v-bus voltage could appear across the 5v or 3.3v mosfet, and that at most 4% of the 12v-bus voltage could appear across the 12v mosfet. the worst-case voltage drop occurs during a 100 s current transient given in the maximum- peak-current column. longer transients may not be tolerable by the mosfet depending on its junction temperature prior to the transient. in most cases, the given mounting-pad area is required to achieve the maximum-average-current rating. it assumes 1- oz. copper, zero air ?w, and an ambient temperature not exceeding 50 o c. the mounting-pad area is the approximate area of a rectangle encompassing the mosfet package and its leads. the r ds(on) numbers assume the device has reached thermal equillibrium at the maximum-average- current. in some cases, the thermal capabilities as well as r ds(on) can be improved by using larger pads, heavier copper, air ?w, or lower ambient temperature. protection from unwanted turn on a dv/dt-activated clamp circuit is internally connected to lgate (pin 4), and is active when the chip is not powered. it is activated when the voltage on either lgate or hgate rises too quickly, and it immediately provides a low- impedance ground path for current from either gate pin. the purpose of the dv/dt-activated clamp circuit is to prevent unwanted turn on of the power mosfets during a hot insertion event. when a device-bay peripheral is inserted into the bay, the power pins on the peripheral are brought into contact with the already-energized mating contacts in the bay. this results in a very fast-rising voltage edge on the drains of the power mosfets which can inject current through the gate-to-drain capacitance and brie? turn on the power mosfet. the result is a momentary dip in the rail voltage which can effect the device s operation as well as the operation of any other device already connected and potentially the host system itself. without the dv/dt-activated clamp, a decoupling capacitor would be needed between each power mosfet drain and ground using up valuable board space and adding unnecessary cost. the HIP1020 solves this problem by providing a path for capacitively- coupled current to reach ground. increasing the rise time the HIP1020 has an internal-ramping charge pump that increases the voltage to the power mosfets in a predictable controlled manner allowing soft turn on of most types of loads. it is possible that some types of load would require slower turn on. this could arise when a load has a large capacitive component or for some other reason requires an extraordinarily high starting current. without the external capacitor, c1 (see figure 1), the ramp rate is about 5v/ms. a capacitor between hgate and ground will slow the rise time of both gate voltages to a rate given by in equation 1, c1 is the value of capacitor in farads required to achieve a rise rate of dv/dt in v/s, and i hgate is current output of pin 4 given in amperes as shown in the ?lectrical speci?ations?section of this data sheet. figures 2 through 5 show gate voltage waveforms for selected values of c1. table 1. device-bay mosfet selection guide for peripheral-power control intersil part no. mounting-pad area (in 2 ) package r ds(on) (m ? ) bus (voltage) maximum average current maximum peak current huf76105dk8 0.05 so-8 dual 63 12 3a (note 4) 7a (note 5) 51 5 1a 2a 48 3.3 1a 1.25a huf76113dk8 0.05 so-8 dual 43 12 3a (note 4) 11a (note 5) or 40 5 2a 2.5a huf76113t3st 0.08 sot223 single 37 3.3 1.5a 1.5a huf76131sk8 0.05 so-8 single 17 12 6a (note 4) 25a (note 5) 16 5 5a (note 4) 6a (note 5) 15 3.3 4a 4a huf76143s3s 0.31 to-263 single 7 3.3 9a (note 4) 9a (note 5) notes: 4. maximum-average-current level meets or exceeds the device-bay specified level for a 30s ?eak? 5. maximum-peak-current level meets or exceeds the device-bay specified level for a 100 s ?ransient? c1 i hgate dv dt ------ ?? ?? --------------------- = (eq.1) HIP1020
6 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com special applications the HIP1020 is well suited to work with n-channel mosfets controlling voltages other than 12v, 5v, or 3.3v provided three basic constraints are observed. the ?st constraint is that the bias voltage for the HIP1020 is either 12v or 5v. chip operation at voltages signi?antly below 5v is not possible, while a bias voltage very much above 12v can unnecessarily stress the part. operation between 5v and 12v can ?onfuse?the chip as it tries to determine whether to operate as a voltage doubler or voltage tripler. the ?al two constraints have to do with proper operation of the power mosfets. these constraints assume that a rail voltage, v rail , is to be switched using an n-channel power mosfet having a gate-to-source breakdown voltage of v br and a threshold voltage of v th . v gate can be either v hgate or v lgate depending on which pin is connected to the power mosfet and will be selected based on which gate voltage is most appropriate for the application. the requirement in equation 2 is necessary to assure that the power mosfet is fully enhanced. v th should be the maximum data-sheet value needed to assure adequately low r dson . the requirement in equation 3 assures that the power mosfet is protected from breakdown of the gate oxide. v th v gate v rail < (eq.2) v br v gate v rail > (eq.3) HIP1020
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